The present invention relates to an image memory system, and more particularly to an image memory system capable of quickly performing a read operation even in case of reading out image data from an image memory consecutively in an arbitrary direction.
In recent years, with the increase of the processing speed of an image processing apparatus, a memory making it possible to quickly read and write image information has been demanded. And as a memory capable of meeting this demand, a high-speed DRAM called a synchronous DRAM or a synchronous graphic RAM is widespread.
Generally, among synchronous DRAMs there is a synchronous DRAM provided with two or more banks each having an independent address space, and such a synchronous DRAM has a feature that its banks can be operated independently of each other. In such a synchronous DRAM, however, the respective banks generally share an address bus, a command bus and a data bus among them.
In some synchronous DRAMs, an address bus and a command bus cannot be logically separated from each other in actual operation. That is to say, when a command is given to such a synchronous DRAM, a part of an address bus may be occupied, and it is not possible to give command data and address data separately. The reason is that address data also can be considered to be a part of command data and it is thought that a practical advantage is not obtained by logically separating them.
In this specification, a command which does not have its exclusive command line but makes a memory perform some operation by combining a plurality of control lines together is also called xe2x80x9ccommandxe2x80x9d.
A synchronous DRAM is provided with a number of commands for operating this DRAM itself, and there are an xe2x80x9cactive commandxe2x80x9d and a xe2x80x9cprecharge commandxe2x80x9d among them. These commands are given to each bank. When an active command is issued, a row address is also given, and therefore when an active command is given, the row address of a cell to be accessed is specified at the same time.
A precharge command is a command for declaring a row space to be closed when an operation of accessing the row space has ended. In order to access a row space and then access another row space belonging to the same bank, it is necessary to perform a precharge operation to said bank before such another accessing operation.
And a synchronous DRAM can perform what is called a burst access operation. That is to say, when a column address is given within some row space to specify one cell, the synchronous DRAM can serially read or write data (for example, data of 8 bits in length) of a plurality of cells having the said cell as the forefront and being consecutive in column address as synchronizing these data with a single clock. Due to this, its operation in case of performing a burst access becomes very fast.
And in case of accessing optional column addresses also, if they are in the same,row space, it can perform a fast access synchronized with a clock by giving consecutively column addresses. This is called a random column access. In case of consecutively accessing addresses in different row spaces, however, its operation speed is of the same degree as an ordinary DRAM.
By the way, the present applicant has proposed an image memory system capable of efficiently reading out image data using a synchronous DRAM having a 2-bank structure as an image memory in. Japanese Patent Provisional Publication No. 106,374/97. In case of storing image data of each dot which constitutes an image, the said image memory system divides the image (for example, a display image composed of 1,024 dots in the x-axis direction and 1,024 dots in the y-axis direction) into a number of blocks (one block contains image data of 16 dots xc3x9716 dots, for example), and makes each block correspond to one row space of a synchronous DRAM and makes blocks being adjacent to each other with a common side between them belong to different banks respectively.
In this case, when coloring the divided blocks by bank (for example, coloring banks at one side with white and banks at the other side with gray), as shown in FIG. 2, one image has a checkered pattern taking a block as a constituent unit. In FIG. 2, as described later, one block is composed of 8 dots xc3x978 dots for convenience of explanation.
In case of storing an image into a synchronous DRAM in such a manner, an operation of reading out this image is as follows. In case of reading out image data of dots consecutively in the x-axis direction (from left to right in FIG. 2), a fast read operation can be performed by a burst access as described above in the same block (these data belong to the same row address).
And in the x-axis direction, in case of reading out image data of dots consecutively over three or more blocks crossing the boundaries of the blocks, namely, in case of accessing a row space belonging to a first bank and then accessing a row space belonging to a second bank and further accessing another row space belonging to the first bank, the operation is as follows.
Image data of blocks adjacent to each other are stored in different banks and it is enough to specify only the forefront address of column addresses in the same row space, and therefore it is possible to perform a precharge operation to a row space of a first bank as accessing a row space belonging to a second bank and further activate another row space of the first bank. Thanks to this, it is not necessary to take the trouble to take a time for precharging and activating the first bank and the time for precharging and activating the first bank results in being hidden seemingly, and therefore an efficient access can be performed.
On the other hand, in case of accessing consecutively image data in the y-axis direction, it is possible to perform a random column access in the same block (namely, in the same row) as described above.
Image data read out from an image memory in this way are stored in a display memory and then are read out from the display memory to be displayed on a display device.
In case of displaying an ordinary image, the image is often read out consecutively along the x-axis or y-axis direction, and in such a case a fast and efficient access can be performed by a burst access as described above.
However, it is not always in the x-axis or y-axis direction that image data of a stored image are read out from an image memory. For example, in case of tilting or turning a displayed object in a polygon drawing operation and the like, it is necessary to read out data of a texture and the like stored in an image memory in an oblique direction. In case of reading out data stored in an image memory in an oblique direction corresponding to the inclination or rotation of an image, storing these data in a display memory in order of reading out, reading out these data from the display memory in order of storing, and displaying them on a display screen, an object seems to tilt or turn on the display screen.
Since an image memory system disclosed in said patent laid-open publication cannot perform a burst access when attempting to read out stored image data in an oblique direction of an image, it is necessary to give a column address to each dot even in the same row space. And in case of accessing consecutively across the boundary between blocks, it is necessary to frequently give an active command or a precharge command, but in an ordinary synchronous DRAM, as described above, since a command bus and an address bus are not separated from each other, a column address cannot be given for a period of giving an active command or a precharge command.
Further, a waiting time to some degree is needed after an active command is issued to a bank until a column address is given to the bank, and after a precharge command is issued to a bank until an active address is given to the same bank.
Therefore, in case of attempting to read out image data in an oblique direction of an image, there is a problem that reading the image data is more delayed in comparison with a case of reading out in the lateral direction in which a burst access can be performed.
The present invention has been made under such a background and an object of the invention is to provide an image memory system capable of efficiently reading out image data even in case of reading out image data from an image memory consecutively along a direction other than the direction in which a burst access can be performed.
In order to attain the above-mentioned object, the present invention is characterized by an image memory system for storing image data related to pixels forming an image, comprising;
first and second memories each having at least two banks in them,
a memory controller for controlling to read or write image data from or into said first and second memories,
a first command address bus provided between said memory controller and the first memory,
a second command address bus provided between said memory controller and the second memory, and
a data bus provided commonly to said first and second memories; wherein
in case that said image is partitioned into square domains each of which is composed of pixels being equal in number to pieces of image data capable of being stored in one row space of said first or second memory and image data of pixels contained in one square domain are made to correspond to one row space, image data of pixels contained in the respective square domains are stored in the first and second memories so that row spaces respectively corresponding to two square domains being adjacent to each other with a common side between them in the image belong to different memories and row spaces respectively corresponding to two square domains having commonly the same vertex and having no common side belong to different banks of the same memory.
As said first and second memories, for example, synchronous DRAMs or synchronous graphic RAMs can be used.
And the present invention is characterized by an image memory system for storing image data related to pixels forming an image, comprising;
first and second memories having at least two banks in them,
a memory controller for controlling to read or write image data from or into said first and second memories,
a first command address bus provided between said memory controller and the first memory,
a second command address bus provided between said memory controller and the second memory, and
a data bus provided commonly to said first and second memories; wherein
in case that one or more square domains are made to be contained in one group when said image is partitioned into groups, and the number of words capable of being stored in one row space of said first and second memories and the number of pixels in said one group are made to be equal to each other, and further image data of every pixel of every square domain in one group are made to correspond to one row space, image data of pixels contained in the respective square domains are stored in the first and second memories so that (a) two square domains being adjacent to each other with a common side between them in the image belong to different memories and two square domains having commonly the same vertex and having no common side in the image belong to different banks of the same memory, or (b) two square domains being adjacent to each other with a common side between them in the image belong to different memories and two square domains having commonly the same vertex and having no common side in the image belong to the same group, or (c) two square domains being adjacent to each other with a common side between them in the image belong to the same group and two square domains having commonly the same vertex and having no common side in the image belong to different banks of the same memory, or (d) two square domains being adjacent to each other with a common side between them in the image belong to the same group and two square domains having commonly the same vertex and having no common side in the image belong to the same group.
Furthermore, the present invention is characterized by an image memory system in which image data related to the respective pixels of an image composed of pixels arranged at positions specified by combination of a row specifying bit string of Ny bits in length and a column specifying bit string of Nx bits in length is stored in specific two memories, wherein;
said respective two memories have 2b (where b is a positive integer) banks capable of being operated independently of each other, make it possible to consecutively access synchronously with a clock a specified number of pieces of data at consecutive addresses in the same row space on the basis of addresses specified by a row address bit string of Nr bits in length and a column address bit string of Nc (Nc=Nx+Nyxe2x88x92Nrxe2x88x92bxe2x88x921) bits in length in a bank specified by a bank changeover bit (or a bank changeover bit string), and have a route selecting bit for specifying a memory to be accessed out of said two memories, and said image memory system comprises;
a means for forming said column address bit string out of the lower L bits of said column specifying bit string and the lower (Ncxe2x88x92L) bits of said row specifying bit string,
a means for forming said row address bit string out of the upper (Nxxe2x88x92Lxe2x88x92Bx) bits of said column specifying bit string and the upper (Nyxe2x80x94Nc+Lxe2x88x92By) bits of said row specifying bit string when Bx ( greater than xe2x88x921) and By ( greater than =1) are arbitrary positive integers satisfying xe2x80x9cBx+By=b+1xe2x80x9d, and
a means for forming a route selecting bit and a bank changeover bit string by using a bit string [bx] of Bx bits from the (L+1)th bit to the (L+Bx)th bit of said column specifying bit string and a bit string [by] of By bits from the (Ncxe2x88x92L+1)th bit to the (Ncxe2x88x92L+By)th bit of said row specifying bit string, wherein;
said route selecting bit is formed out of the exclusive OR of the (L+1)th bit of said column specifying bit string and the (Ncxe2x88x92L+1)th bit of said row specifying bit string, and
said bank changeover bit string is formed out of a bit string obtained by removing either one bit of the (L+1)th bit of said column specifying bit string or the (Ncxe2x88x92L+1)th bit of said row specifying bit string, which are used for forming said route selecting bit, from a bit string obtained by combining both of said bit strings [bx] and [by] together.
And the present invention is characterized by an image memory system in which image data related to the respective pixels of an image composed of pixels arranged at positions specified by combination of a row specifying bit string of Ny bits in length and a column specifying bit string of Nx bits in length is stored in specific two memories, wherein;
said respective two memories have first and second banks capable of being operated independently of each other, make it possible to consecutively access synchronously with a clock a specified number of pieces of data at consecutive addresses in the same row space on the basis of addresses. specified by a row address bit string of Nr bits in length and a column address bit string of Nc (Nc=Nx+Nyxe2x88x92Nrxe2x88x922) bits in length in said first bank or second bank specified by a bank changeover bit, and have a route selecting bit for specifying memory to be accessed out of said two memories, and said image memory system comprises;
a means for forming said column address bit string out of the lower L bits of said column specifying bit string and the lower (Ncxe2x88x92L) bits of said row specifying bit string,
a means for forming said row address bit string out of the upper (Nxxe2x88x92Lxe2x88x921) bits of said column specifying bit string and the upper (Nyxe2x88x92Nc+Lxe2x88x921) bits of said row specifying bit string,
a means for taking as said route selecting bit the exclusive OR of the (L+1)th bit of said column specifying bit string and the (Ncxe2x88x92L+1)th bit of said row specifying bit string, and
a means for taking as said bank changeover bit the (L+1)th bit of said column specifying bit string or the (Ncxe2x88x92L+1)th bit of said row specifying bit string.